chArm-v3 CPU Pipeline & Cache Simulator

Overview

A cycle-accurate simulator for a pipelined 64-bit instruction set architecture, modeling CPU execution, hazard resolution, and a two-level memory hierarchy. Built to explore how pipeline control and cache behavior impact correctness and performance.

Highlights

• Built emulated hardware components including an ALU, register file, and condition logic, then integrated them into a multi-stage PIPE CPU simulator.
• Implemented hazard detection and resolution mechanisms (stalling, squashing, forwarding) to correctly handle data and control dependencies.
• Designed and integrated a write-back, write-allocate cache simulator with LRU replacement, modeling variable memory latency and its impact on pipeline performance.
• Debugged and validated the system against reference binaries and trace-driven test suites.